Reliable software for unreliable hardware: Embedded code generation aiming at reliability”, Codess+ISSS

A compilation technique for reliability-aware software transfor-mations is presented. An instruction-level reliability estimation technique quantifies the effects of hardware-level faults at the instruction-level while considering spatial and temporal vulnera-bilities. It bridges the gap between hardware – where faults occur according to our fault model – and software (the abstraction level where we aim to increase reliability). For a given tolerable per-formance overhead, an optimization algorithm compiles an appli-cation software with respect to a tradeoff between performance and reliability. Compared to performance-optimized compilation, our method incurs 60%-80 % lower application failures, averaged over various fault injection scenarios and fault rates